1. Field of the Invention
The present invention relates to a method of fabricating integrated circuit device, and more particularly, to a method of fabricating a complementary metal-oxide-semiconductor (CMOS) transistor and a metal-oxide-semiconductor (MOS) transistor.
2. Description of Related Art
Metal-oxide-semiconductor (MOS) transistor is a basic device in logic circuits. Each transistor comprises a gate, a source/drain (S/D) region in the substrate on two sides of the gate, and a channel between the source region and the drain region. When the manufacturing of MOS transistor is progressed into the micrometer level, short channel effect and hot carrier effect is intensified due to the shortening of the channel between source/drain regions. The short channel effect and hot carrier effect is so devastating that the device can hardly operate normally. Therefore, a lightly doped drain (LDD) structure is often introduced into the design of the source/drain regions of a transistor for processes at the micrometer level or below. In other words, a lightly doped drain region having the same doping state as the source/drain region but a shallower depth is formed under the gate structure adjacent to the source/drain region so that the electric field in the channel is lowered and short channel effect and hot carrier effect is avoided.
In general, devices with different functions, for example, input/output (I/O) transistors (serving as on/off switches) and core transistors, are disposed on the same chip. According to their sizes, the I/O transistors are classified as large devices and the core transistors are classified as small devices.
However, as the size of MOS transistors drops below the deep sub-micron level, the size of core transistors is reduced with each advance in the processing technique but the size of the I/O transistors is almost unchanged. As a result, for the LDD structure in devices having a different size, the range of diffusion in a subsequent annealing process must be carefully controlled. Otherwise, the diffusion regions in the LDD structures of the devices may be either too large or too small due to their different sizes. An inappropriately fabricated diffusion region in the LDD structure may affect the electrical properties of the device and lead to device failure. In particular, since the dimension of each device is already so small, too much lateral diffusion will lead to short channel effect or punch through problems. On the other hand, for larger devices, too little lateral diffusion will lead to a high impedance at the overlapping region between the LDD and the gate, thereby lowering the saturated drain current and affecting the performance of the device.
In addition, a few other U.S. Patents, for example, U.S. Pat. No. 5,726,071, U.S. Pat. No. 6,458,643, U.S. Pat. No. 6,797,593 and U.S. Pat. No. 6,559,015, have also disclosed some related techniques and can serve as reference material in the present invention.
At present, with the rapid development of semiconductor processes, an efficient method of producing LDD structures suitable for devices of different dimensions on a wafer is one of the most important issues.